Article ID: 000085464 Content Type: Troubleshooting Last Reviewed: 11/25/2013

Long Term CK Jitter Exceeds Spec in HPS Memory Interface in Arria V and Cyclone V Devices

Environment

  • Quartus® II Subscription Edition
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    Critical Issue

    Description

    This problem affects DDR2, DDR3, and LPDDR2 products.

    DDR2, DDR3, and LPDDR2 interfaces using the HPS memory interface on Arria V or Cyclone V devices, produce a long term CK jitter (on the HPS side, not the FPGA side) that exceeds the JEDEC and vendor specification (tERR(Nper) for moderate values of N).

    Resolution

    Altera has verified that adherence to this spec is not required, provided that short-term jitter (tJITcc and tJITper) requirements are met. In the configurations described, tJITcc and tJITper are within the JEDEC specifications.

    This issue will not be fixed.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs

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