This problem affects DDR2, DDR3, and LPDDR2 products.
DDR2, DDR3, and LPDDR2 interfaces using the HPS memory interface
on Arria V or Cyclone V devices, produce a long term
(on the HPS side, not the FPGA side) that exceeds the JEDEC and
vendor specification (
Nper) for moderate
Altera has verified that adherence to this spec is not required,
provided that short-term jitter (
requirements are met. In the configurations described,
within the JEDEC specifications.
This issue will not be fixed.