Article ID: 000085463 Content Type: Error Messages Last Reviewed: 08/27/2013

Warning: Clock period specified for PLL output clock <PLL output clock> must be greater than or equal to <clock period> for output I/O <PLL output clock>.

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You might get this warning message if your design is using an advanced clock scheme that the classic timing analyzer does not support. The warning message can occur for example, if you implement your design with the Triple-Speed Ethernet megafunction and are using the Classic Timing Analyzer during compilation.

In order to avoid this warning message, do use the TimeQuest Timing Analyzer in the timing analysis process.  The Classic Timing Analyzer was last supported in the Quartus® II software version 10.0.

Related Products

This article applies to 1 products

Cyclone® III FPGAs

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