Article ID: 000085434 Content Type: Troubleshooting Last Reviewed: 06/01/2015

Why does my Stratix IV device, PCI Express Gen2 system fail to link train after upgrading to Quartus II software versions 14.0 and later?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a bug in the Quartus® II software versions 14.0 and later, your Stratix® IV device, PCI Express® Gen2 system may fail to link train under the following conditions.

    • Instantiating a new Gen2 Hard IP for PCI Express generated in Quartus II software versions 14.0 and later.
    • Upgrading an existing Gen2 Hard IP for PCI Express regenerated in Quartus II software versions 14.0 and later.
    • Instantiating a new Gen2 PIPE PHY IP generated in Quartus II software versions 14.0 and later.
    • Upgrading an existing Gen2 PIPE PHY IP regenerated in Quartus II software versions 14.0 and later.
    Resolution

    To solve this problem you can add the following assignments to your Quartus Settings File (.QSF)

    • set_instance_assignment -name POWER_UP_LEVEL HIGH -to *pllreset_delay_blk0c*
    • set_instance_assignment -name POWER_UP_LEVEL HIGH -to *pcie_sw_sel_delay_blk0c*

    Related Products

    This article applies to 2 products

    Stratix® IV GT FPGA
    Stratix® IV GX FPGA

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