Why does my RTL inferred RAM use more registers in the Quartus II software version 13.1 than in previous versions?

Due to a problem in the Quartus® II software version 13.0 SP1 and earlier, you may see a reduced number of registers when inferring a RAM from raw logic with non-zero power-up values as these were ignored and the post fit netlist did not match the RTL.

In the Quartus II software version 13.1 and later these bits are implemented as registers instead of RAM blocks.

To avoid using more registers, perform one of the following options:

• Do not use any non-zero power-up values
• Instantiate the RAM with a Memory Initialization File (.mif)
• Infer the RAM as an array of std_logic_vectors