Article ID: 000085418 Content Type: Troubleshooting Last Reviewed: 07/01/2013

DDR2 Interfaces on Cyclone V SoC Devices May Fail Read Capture Timing

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

This problem affects DDR2 products.

DDR2 interfaces on Cyclone V SoC devices may fail Read Capture Timing in Report DDR.

Resolution

The workaround for this issue is to choose a faster speed grade DDR2 device.

This issue will be fixed in a future version.

Related Products

This article applies to 1 products

Cyclone® V FPGAs and SoC FPGAs

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.