Article ID: 000085414 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Does the 10-Gigabit Ethernet Reference Design reset sequence take into account offset cancellation?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, the 10-Gigabit Ethernet Reference Design reset sequence does not take into account offset cancellation.

Offset cancellation occurs once after device power up. In order to account for offset cancellation on Stratix® IV GX and Arria® II GX devices you must monitor the output busy signal of the altgx_reconfig Megawizard® Plugin Manager. You must design your logic to hold the 10-Gigabit Ethernet Reference Design in reset until the busy signal goes low.

For more information on the offset cancellation function please refer to the Stratix IV GX and Arria II GX Device Handbooks.

Related Products

This article applies to 3 products

Arria® II GX FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA

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