Article ID: 000085413 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Why do I get compilation error when I select clk [1] through [9] as the input clock source for the ATX_PLL in the MegaWizard?

Environment

  • Stratix® IV FPGAs
  • Stratix® IV GX FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The ALTGX Megawizard allows maximum of 10 input reference clocks as sources to the ATX_PLL. When the user selects values from 1 through to 9 for the ATX PLL in the ‘What is the selected input clock source for the Rx/Tx PLLs?’ option the design fails compilation. Quartus® II software will produce an error saying for example that inclk [1] of ATX PLL cannot be connected.

The following workaround is required

- Select ‘0’ as the input clock source for the ATX PLL and

-  Connect the pll_inclk_rx_cruclk [0] as the input clock source for the ATX PLL in your design

This problem occurs in Quartus® II software version 9.1 and is scheduled to be fixed Quartus® II software version 9.1 SP1.

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