Article ID: 000085387 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why do I see discontinuity in the read data burst on mem_dq bus even when I do not change the row address during the read operation using DDR3 SDRAM UniPHY and Altmemphy based controller?

Environment

    Quartus® II Subscription Edition
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When implementing DDR3 SDRAM UniPHY and Altmemphy based memory controller, user will notice that during read operation, mem_dq bus does not give continuous burst even when there is no row address change. You will see this behavior in simulation as well.

Resolution

You need to manually update CFG_RDBUFFER_ADDR_WIDTH in alt_mem_ddrx_controller.v HDL to fix it.

Set CFG_RDBUFFER_ADDR_WIDTH to:
Full rate - 8
Half rate - 7
Quarter rate - 6

This issue will be fixed in a future version of the Quartus® II software.

Related Products

This article applies to 8 products

Stratix® V GX FPGA
Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® IV E FPGA
Stratix® V GT FPGA
Stratix® V E FPGA
Stratix® V GS FPGA

1

Need more help?

Contact support

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.