Article ID: 000085379 Content Type: Troubleshooting Last Reviewed: 12/31/2013

Error (21087): Input port "CALCLK" must be driven by the same source

Environment

  • Stratix® V GX FPGA
  • Arria® V GX FPGA
  • Arria® V GT FPGA
  • Stratix® V GS FPGA
  • Stratix® V GT FPGA
  • Cyclone® V GX FPGA
  • Cyclone® V GT FPGA
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You will see this error on Stratix® V, Arria® V, or Cyclone® V transceiver devices if you have more than one reconfiguration controller with different clock sources for the mgmt_clk_clk port if they share a single calibration block.

The number of calibration blocks is device dependent.

Resolution To work around this problem, use a common mgmt_clk_clk.

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