Article ID: 000085369 Content Type: Troubleshooting Last Reviewed: 08/07/2023

Why does the Hard IP for PCI Express 128-bit Avalon-MM TX interface not transmit packets in simulation?

Environment

  • Quartus® II Subscription Edition
  • Simulation
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    When simulating the Hard IP for PCI Express® 128-bit Avalon-MM interface in the Quartus® II software version 14.0 and earlier, the device under test (DUT) is not able to transmit any packets from the Avalon-MM bus to the PCIe link.

    This problem is caused by the incorrect width declaration of control signals in the transmit data path. The control signals are declared as 5-bits, but only 4-bits are driven in the testbench.  The most significant bit is not driven and becomes "x" in simulation.

     

    Resolution

    To work around this problem, follow the steps below:

    1. Open the file altpciexpav128_cr_rp.v
    2. Find the lines
      • wire [4:0] tx_low64_fifo_wrusedw
      • wire [4:0] tx_hi64_fifo_wrusedw
    3. Change the lines to
      • wire [3:0] tx_low64_fifo_wrusedw
      • wire [3:0] tx_hi64_fifo_wrusedw

    The problem is scheduled to be fixed in a future release of the Quartus® II software.

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    This article applies to 15 products

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