Article ID: 000085364 Content Type: Troubleshooting Last Reviewed: 09/11/2012

What is the behavior of the phase-locked loop (PLL) output clock(s) if the input clock is disabled while the device is in user mode for my APEX™ 20KE or APEX 20KC device?


  • PLL
    Description If you remove the input clock, the PLL drifts to the voltage-controlled oscillator's (VCO's) lower frequency limit (200 MHz). The VCO will continue to run at some unspecified floor frequency. The PLL output clock(s) is then equal to the VCO floor frequency divided by K or V, which are the output dividers for the two PLL clock outputs clock0 and clock1.

    The VCO's floor frequency limit can extend below 200 MHz depending on process, voltage, and temperature. Therefore, the VCO's floor frequency limit can vary fromlot-to-lot. While Altera specifies a minimum VCO frequency, the output frequency of the clock cannot be guaranteed if the input clock has been removed.

    When the input clock is disabled, the PLL will lose lock and the LOCK pin will go low. Once an input clock is re-applied, the PLL will re-lock onto the clock signal and the lock period time must be allowed to ensure the PLL has regained lock.

    During simulation in the Altera® Quartus® II software, the PLL clock output(s) will be low because the simulator cannot model the frequency drift. The LOCK pin will also be low at this time. Once the input clock is re-applied again, the PLL clock output(s) will begin to toggle in simulation.

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    Apex™ 20K