Article ID: 000085363 Content Type: Troubleshooting Last Reviewed: 06/04/2013

What are the active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix V, Arria V, and Cyclone V transceiver devices?

Environment

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Description

The active bit mappings of the Native PHY rx_parallel_data and tx_parallel_data busses when the "Enable simplified data interface" is disabled for Stratix® V, Arria® V, and Cyclone® V transceiver devices is listed in the transceiver Native PHY Megawizard™ message pane.

 

Related Products

This article applies to 13 products

Stratix® V GX FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Stratix® V GT FPGA
Cyclone® V GX FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V ST SoC FPGA
Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA

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