Altera DSP Builder Advanced Internal Restriction: 'blockMap.find(fu->GetName()) == blockMap.end()' in d:/SJ/nightly/12.0/178/w32/p4/ip/aion/src/mip_common/hw_model_dup_remover.cpp:191.
As an example, if you have two blocks in your design inside a scheduled subsystem:-
psc_ctrl_fixed/FIX_MCTRL/Fix_Mtr_Ctrl1_DSPBA/Current_DSPBA/T/KU1/Mult
psc_ctrl_fixed/FIX_MCTRL/Fix_Mtr_Ctrl1_DSPBA/Current_DSPBA/T/-KU1/Mult
These are internally converted into flat names at the level of the scheduled subsystem:-
Fix_Mtr_Ctrl1_DSPBA_Current_DSPBA_T_KU1_Mult
Fix_Mtr_Ctrl1_DSPBA_Current_DSPBA_T_-KU1_Mult
Most non-alphanumeric characters are not legal in VHDL symbols and so they are converted into underscores:-
Fix_Mtr_Ctrl1_DSPBA_Current_DSPBA_T_KU1_Mult
Fix_Mtr_Ctrl1_DSPBA_Current_DSPBA_T__KU1_Mult
Double underscores are also not legal in VHDL symbols and so they are collapsed into single underscores:-
Fix_Mtr_Ctrl1_DSPBA_Current_DSPBA_T_KU1_Mult
Fix_Mtr_Ctrl1_DSPBA_Current_DSPBA_T_KU1_Mult
The two symbol are now identical, which causes an internal error inside the DSPBA pipeline.
The workaround is to avoid using non-alphanumeric characters to distinguish subsystems at the same level from each other.