This error may be seen during simulation of Altera PLL Megafunctions generated in VHDL from the Quartus® II software version 12.1, when physical output clock parameters are enabled in the MegaWizard™ and a Fractional Multiply Factor (k) has been specified.
To work around this problem in the Quartus II software version 12.1, Altera PLL Megafunctions should be generated in Verilog if manual setting of Fractional Multiply Factor (k) is required.
This problem is scheduled to be fixed in a future release of the Quartus II software.