Description
This error may occur when simulating Nios® II 1.1 VHDL designs which contain multiple clock domains in the ModelSim® tool. Verilog systems which contain multiple clock domains will simulate without errors.
The workaround involves modifying the VHDL source code generated by SOPC Builder. Browse to the line number in the VHDL source code that generates the error in the ModelSim tool. The error is caused by the assignment to the 'data_in' bus in a component instantiation. The source code which generates the error will resemble the following:
data_in => std_logic_vector("0000000000000000") & (slave_address);
In order to fix the problem you will need to create a new internal signal at the same level as the component instantiation. For example, create a signal called "internal_slave_address". Then assign the following:
internal_slave_address <= std_logic_vector("0000000000000000") & (slave_address);
and change the port mapping in the component instantition to read as follows:
data_in => internal_slave_address;
This problem has been fixed in Nios II 5.0.