Article ID: 000085296 Content Type: Troubleshooting Last Reviewed: 10/01/2013

Why am I seeing incorrect output clock frequencies when simulating the Altera_PLL megafunction?

Environment

    Quartus® II Subscription Edition
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Description Due to a bug in the simulation models in the Quartus® II software through version 12.0, if you have multiple output clocks enabled in the Altera_PLL megafunction, the simulation results may show incorrect output frequencies.  This only affects the calculation of the output clock frequency in simulation, hardware is not affected.
Resolution This issue is fixed in the Quartus II software version 12.0sp1.

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