Article ID: 000085281 Content Type: Troubleshooting Last Reviewed: 08/12/2013

What is the correct flash offset when using the Stratix V GX FPGA Development Kit?

Environment

  • Quartus® II Subscription Edition
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    Description

    When following, "Creating Flash Files Using the Nios® II EDS" flow in the Stratix® V GX FPGA Development Kit User Guide, the following command is given:

    sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020A0000 --pfl --optionbit=0x00030000 --programmingmode=PS

    However, the Address Range given for User hardware 1 in Table A-1 Byte Address Flash Memory Map is:

    0x020C.0000 to 0x0413.FFFF

    Hence the offset shown in the above command is incorrect.

    Resolution

    To correctly generate flash files, use the command below:

    sof2flash --input=<yourfile>_hw.sof --output=<yourfile>_hw.flash --offset=0x020C0000 --pfl --optionbit=0x00030000 --programmingmode=PS

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA

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