Article ID: 000085277 Content Type: Product Information & Documentation Last Reviewed: 06/10/2022

How can I enable HPS User Clock 2 in the Intel® Quartus® II software version 14.1?

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem in the Intel® Quartus® II software version 14.1, HPS User Clock 2 cannot be enabled from the HPS Megawizard in Qsys.

    Resolution

    To work around this issue in the Intel® Quartus® II software version 14.1 follow the steps below:

    To Enable HPS User Clock 2

    1. Save your Qsys project, and exit Qsys
    2. Open the .qsys file containing the HPS instance in a text editor <project Name>.qsys
    3. Search for the parameter S2FCLK_USER2CLK_Enable, and set it to true
      <parameter name="S2FCLK_USER2CLK_Enable" value="true" />
    4. Save the .qsys file
    5. Open the project in Qsys and Generate the System

     Note: The steps above may need to be repeated if the HPS parameters are edited in Qsys.

    To set the frequency of HPS User Clock 2

    The frequency of HPS User Clock 2 must be manually set,  following the Preloader Custom Clocking flow as used for the Quartus II software 13.1 and earlier.   This flow updates the generated BSP handoff file software/<bsp name>/generated/pll_config.h

    Please see the following Rocketboards page for more details: http://www.rocketboards.org/foswiki/Documentation/PreloaderClockingCustomization131

    Then a clock constraint like the below should be added to any .sdc file. Make sure that the .sdc file should be sourced after the .qip file.

    create_clock -period <HPS User Clock 2 period> [get_pins -compatibility_mode *|fpga_interfaces|clocks_resets|h2f_user2_clk]

    This problem is scheduled to be fixed in a future release of the Intel® Quartus® II Software

    Related Products

    This article applies to 5 products

    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Cyclone® V SX SoC FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA

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