Article ID: 000085273 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does "fixedclk_locked" signal keep low when "Enable Configuration via the PCIe link" parameter in MegaWizard window of PCIe is enabled?

Environment

  • Quartus® II Subscription Edition
    • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    The "Configuration via the PCIe® Link (CvP)" feature is not available in Quartus® II version 11.1 yet.  If you turn on the option in PCIe MegaWizard™ window for Stratix® V, incomplete RTLs are generated and it causes "fixedclk_locked" signal to be tied low.

    To prevent this issue, you must turn off "Enable Configuration via the PCIe Link" parameter in PCIe MegaWizard window. This issue will be fixed in the future release.

    Related Products

    This article applies to 2 products

    Stratix® V FPGAs
    Stratix® V GX FPGA

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