Description
Altera
® recommends that I/O cell register assignments are made in the Quartus
™ software. However, you can implement these assignments in Synplify as well using the
syn_useioff attribute on a global or local basis.
You can set this globally by setting syn_useioff=1 on the top level, directly in the source code, through the Synplify settings tool SCOPE, or directly in the constraint file.
| Table 1. Setting syn_useioff=1 Globally |
| Programming Language | Syntax |
| Verilog HDL | module test (d, clk, q) /*synthesis syn_useioff=1 */; |
| VHDL | architecture rtl of test is
attribute syn_useioff : boolean;
attribute syn_useioff of rtl: architecture is true; |
| Constraint file | define_global_attribute syn_useioff 1 |
| Table 2. Setting syn_useioff=1 Locally |
| Programming Language | Syntax |
| Verilog HDL | module test (d, clk, q);
input [3:0] d;
input clk;
output [3:0] q /*synthesis syn_useioff=1 */
reg q;
... |
| VHDL | entity test is
port (d: in std_logic_vector [3 downto 0];
clk: in std_logic;
q : out std_logic_vector[3 downto 0];
attribute syn_useioff : boolean;
attribute syn_useioff of q : signal is true;
end test; |
| Constraint file | define_attirbute {p:q[3:0]} syn_useioff 1 |