Article ID: 000085267 Content Type: Troubleshooting Last Reviewed: 09/12/2012

Can reconfg_clk port of reconfiguration module be drived by ref_clk?

Environment

  • PCI Express
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    If you use the Stratix V Hard IP with CVP, reconfig_clk is required to be the same as refclk for CVP. For non-CVP, it can be derived from a separated free running clock source.

    Resolution

     

    Related Products

    This article applies to 1 products

    Stratix® V GX FPGA

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