Article ID: 000085240 Content Type: Troubleshooting Last Reviewed: 06/30/2014

Why can't I place a reference clock for transceivers on the GXB_RX / GXB_REFCLK input?

Environment

    Quartus® II Subscription Edition
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Description Stratix® V, Arria® V, and Cyclone® V devices support placing an incoming dedicated transceiver reference clock on dual-use GXB_RX / GXB_REFCLK input pins. However, this functionality was not enabled until Quartus® II software version 12.1.  Prior to Quartus II v12.1 reference clocks could only be placed on the dedicated REFCLK input pins.
Resolution This functionality has been fully implemented as of Quartus II v12.1.

Related Products

This article applies to 14 products

Cyclone® V SX SoC FPGA
Stratix® V FPGAs
Cyclone® V GT FPGA
Stratix® V GX FPGA
Cyclone® V GX FPGA
Stratix® V GT FPGA
Stratix® V GS FPGA
Arria® V GZ FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA
Arria® V GX FPGA
Arria® V FPGAs and SoC FPGAs
Arria® V GT FPGA
Cyclone® V FPGAs and SoC FPGAs

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