Critical Issue
Description
If you compile a UniPHY-based example design in the Quartus II software, TimeQuest may produce warning messages similar to the following:
Warning: Ignored filter at altera_reset_controller.sdc
(17): *|alt_rst_sync_up1|altera_rest_synchronizer_int_chain*|aclr
could not be matched with a pin Warning: Ignored set_false_path
at altera_reset_controller.sdc (17): Argument <from> is an empty
collection
Resolution
You may safely ignore these warning messages. To prevent these
warning messages from appearing, you can modify the Qsys-generated
Synopsys Design Constraints file altera_reset_controller.sdc so
that the paths mentioned in the warnings conform to the specific
hierarchy of your design. (Be aware that any changes that you make
to the .sdc file might be overwritten if you regenerate your IP
core.)