Article ID: 000085225 Content Type: Troubleshooting Last Reviewed: 08/03/2023

Why does the Triple Speed Ethernet MegaCore Function not generate XOFF / XON pause frames even when the XOFF / XON registers or XOFF / XON I/O pins are asserted?

Environment

  • Quartus® II Subscription Edition
  • Triple-Speed Ethernet Intel® FPGA IP
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    Description

    Due to an issue with the Triple Speed Ethernet MegaCore® function, XON / XOFF pause frames may not be generated if you disable the Enable MAC 10/100 half duplex support option.

     

    Resolution

    Turn on the Enable MAC 10/100 half duplex support option in MegaWizard™ Plug-in Manager to workaround this issue. 

    This issue has already been fixed in the Quartus II software version 15.0.1.

    Related Products

    This article applies to 26 products

    Cyclone® IV GX FPGA
    Cyclone® III FPGAs
    Cyclone® IV E FPGA
    Arria® V GX FPGA
    Cyclone® V GT FPGA
    Cyclone® III LS FPGA
    Cyclone® V E FPGA
    Cyclone® V GX FPGA
    Arria® V GT FPGA
    Arria® V GZ FPGA
    Arria® V ST SoC FPGA
    Arria® V SX SoC FPGA
    Arria® II GZ FPGA
    Cyclone® V SE SoC FPGA
    Cyclone® V ST SoC FPGA
    Cyclone® V SX SoC FPGA
    Stratix® II FPGAs
    Stratix® II GX FPGA
    Stratix® III FPGAs
    Stratix® IV E FPGA
    Stratix® IV GT FPGA
    Stratix® IV GX FPGA
    Stratix® V E FPGA
    Stratix® V GS FPGA
    Stratix® V GT FPGA
    Stratix® V GX FPGA

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