Article ID: 000085211 Content Type: Troubleshooting Last Reviewed: 01/01/2015

Are there any guidelines for the parallel flash to Cyclone III connection on the Active Parallel (AP) Interface?

Environment

  • Quartus® II Subscription Edition
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    Description

     

     

     

     

     

     

    For single and multi-device AP configuration, the board trace length and loading between the supported parallel flash and Cyclone® III device should follow these recommendations in Table 1. These recommendations also apply to AP configuration with multiple bus master.

     

    Table 1: Maximum trace length and loading for AP configuration

    Cyclone III

    AP Pins

    Maximum Board Trace Length from Cyclone III device to flash device

    (inches)

    Maximum Board Load

    (pF)

    DCLK

    6

    15

    DATA[15..0]

    6

    30

    PADD[23..0]

    6

    30

    nRESET

    6

    30

    Flash_nCE

    6

    30

    nOE

    6

    30

    nAVD

    6

    30

    nWE

    6

    30

    RDY

    6

    30

     

    For multiple bus master interface,refer to Figure 1 for the recommended routing to minimize signal integrity issue.

     

    Figure 1

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

     

    Related Products

    This article applies to 1 products

    Cyclone® III FPGAs

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