Article ID: 000085203 Content Type: Error Messages Last Reviewed: 09/11/2012

Error: The Quartus II software does not currently support the generation of EDA simulation or timing analysis netlists for Stratix IV designs with transceiver blocks

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

The Quartus® II software version 8.0 does not support  the generation of EDA simulation netlists for Stratix®  IV device designs with transceiver blocks. 

 

To prevent this error, turn off EDA simulation netlist generation as follows:

  1. On the Assignments menu, choose Settings.
  2. Under EDA Tool Settings, choose Simulation.
  3. Click More Settings and set Generate netlist for functional simulation only to Off.

To simulate your design, use the ALTGX.vhd or the ALTGX.v file for functional simulation along with the Quartus II version 8.0 simulation libraries.

Related Products

This article applies to 1 products

Stratix® IV GX FPGA

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