Article ID: 000085161 Content Type: Troubleshooting Last Reviewed: 10/12/2011

Any top or bottom central PLL in Stratix V ES devices that has its reference clock fed by a clock network should not be fed a clock faster than 400 MHz

Environment

  • Quartus® II Subscription Edition
  • PLL
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    Any top or bottom central PLL in Stratix V ES devices that has its reference clock fed by a clock network should not be fed a clock faster than 400 MHz.

    Resolution

    If possible, directly feed the reference clock from a pin or manually place the PLL on the left or right side.

    Related Products

    This article applies to 1 products

    Stratix® V FPGAs

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