Article ID: 000085143 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Does manual clock switchover and manual override operate correctly when neither of the PLL input clocks are toggling in Cyclone III devices?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, manual clock switchover and manual override operate correctly only when PLL inputs inclk0 and inclk1 are both toggling in Cyclone® III devices. The PLL needs both clock edges of inclk0 and inclk1 to change input clock from the primary clock to the secondary clock.

This applies to all device families that support manual clock switchover.

Related Products

This article applies to 10 products

Cyclone® III FPGAs
Cyclone® II FPGA
Stratix® FPGAs
Stratix® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® IV GX FPGA
Stratix® III FPGAs
Stratix® IV GT FPGA
Stratix® IV E FPGA

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