Article ID: 000085135 Content Type: Troubleshooting Last Reviewed: 08/04/2023

When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block?

Environment

    Quartus® II Software
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see timing violations between the ports on the MPFE block using different clock frequencies because the Quartus®II software does not automatically cut these timing paths.

 

 

Resolution

There are no paths between the MPFE ports in the UniPHY-based hard memory controller. The failing paths can be safely cut using either the set_clock_groups or set_false_path SDC commands. Refer to the Quartus® II TimeQuest Timing Analyzer (.PDF) document for more information on the SDC commands.

Related Products

This article applies to 10 products

Arria® V GT FPGA
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Cyclone® V SX SoC FPGA
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Cyclone® V GX FPGA
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Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA

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