Article ID: 000085135 Content Type: Troubleshooting Last Reviewed: 09/28/2015

When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

You may see timing violations between the ports on the MPFE block using different clock frequencies, because these timing paths are not automatically cut by the Quartus II software.

Resolution

There are no paths between the MPFE ports in the UniPHY-based hard memory controller. The failing paths can be safely cut using either the set_clock_groups or set_false_path SDC commands. Refer to the Quartus II TimeQuest Timing Analyzer (.PDF) document for more information on the SDC commands.

Related Products

This article applies to 10 products

Arria® V GT FPGA
Arria® V ST SoC FPGA
Cyclone® V E FPGA
Cyclone® V SE SoC FPGA
Cyclone® V SX SoC FPGA
Cyclone® V GT FPGA
Cyclone® V GX FPGA
Arria® V GX FPGA
Arria® V SX SoC FPGA
Cyclone® V ST SoC FPGA

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