Article ID: 000085128 Content Type: Troubleshooting Last Reviewed: 08/17/2012

Are there any conditions where the transceiver CMU PLL may fail to lock after CMU PLL reconfiguration in Stratix IV GX/GT, HardCopy IV GX, and Arria II GX/GZ devices?

Environment

  • HardCopy™ IV GX ASIC Devices
  • Arria® II GZ FPGA
  • Arria® II GX FPGA
  • Stratix® IV GT FPGA
  • Stratix® IV GX FPGA
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Description

Yes, the transceiver CMU PLL may fail to lock on Stratix® IV GX/GT, HardCopy® IV GX, and Arria® II GX/GZ devices after CMU PLL dynamic configuration in the following specific corner case.

  • Using non-dedicated REFCLK pins to clock the CMU PLL
    • REFCLK pins from outside the transceiver block via an ITB line
    • Clock output ports from left/right GPLLs (PLL cascading)
    • Dedicated CLK input pins through GCLK network

and

  • Hard-wiring the ALTGX_RECONFIG MegaWizard® reconfig_mode_sel port to a fixed value of 3'b100 (CMU PLL reconfiguration mode).

This problem is not seen in simulation.

This problem is present in all Quartus® II software versions up to and including Quartus II 10.1.

To correct this problem you must install Quartus II software version 10-1-SP1, and regenerate your ALTGX_RECONFIG Megawizard component.

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