Article ID: 000085122 Content Type: Troubleshooting Last Reviewed: 02/05/2014

Arria V GZ and Stratix V PCI Express Hard IP does not reject coefficient requests properly

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

If the Arria® V GZ or Stratix® V Hard IP for PCI Express® receives an illegal coefficient request from a link partner during either equalization phase 2 or 3, the IP rejects it. Per specification, the IP should send out two consecutive identical TS1's with the reject bit set and with the rejected coefficient values.

The Hard IP does not do this. Instead, it sends out TS1s with the reject bit set all the time, and the coefficient value in the second TS1 do not match the reject values.

This issue can be seen in simulation and hardware. In hardware, if the link partner requests valid coefficients according to specification, the problem will not be observed.

Resolution

As a work around ensure that the link partner follows the specification and requests valid coefficients during equalization phases.

Related Products

This article applies to 4 products

Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA
Arria® V GZ FPGA

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