Article ID: 000085101 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Can I use the external PLL option when implementing the altlvds megafunction with a deserialization factor of 2?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No, when you have a deserialization factor of 2, the SERDES is bypassed and the functionality is implemented in double data rate (DDR) registers. You need at least a deserialization factor of 4 to use the external PLL option. 

Related Products

This article applies to 2 products

Stratix® II FPGAs
Stratix® II GX FPGA

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