Article ID: 000085080 Content Type: Troubleshooting Last Reviewed: 09/08/2014

Why do I see warning messages when simulating a Native PHY with 10G PCS PRBS pattern generator and verifier enabled on Arria V GZ or Stratix V GX devices?

Environment

  • Arria® V GZ FPGA
  • Stratix® V GS FPGA
  • Stratix® V GX FPGA
  • Stratix® V GT FPGA
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Description

You may see the following warnings when simulating a Native PHY with 10G PCS PRBS pattern generator and verifier enabled on Arria® V GZ or Stratix® V GX devices.

#  ** Warning: Attempting to read from an invalid address 15e
#  ** Warning: Attempting to write to a reserved register at address 15e
#  ** Warning: Attempting to read from an invalid address 164
#  ** Warning: Attempting to write to a reserved register at address 164

These addresses are valid for the 10G RX PCS, however the 10G TX PCS simulation models incorrectly check these addresses. As they aren't valid in the 10G TX PCS space and they are flagged as invalid.

Resolution

These warnings do not restrict reading and writing from these registers, and are safe to ignore.

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