Article ID: 000085064 Content Type: Troubleshooting Last Reviewed: 10/01/2013

What is the cyclic redundancy check (CRC) calculation time formula for different values of n (where n is the number of divisor)?

Environment

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Description

The handbooks for Cyclone® III, Cyclone IV, Cyclone V,  Arria® II, Arria V, Stratix® IV, and Stratix V devices show the maximum and minimum CRC calculation time. Refer to the Single Event Upset (SEU) Mitigation chapter of the respective device family handbook for the maximum and minimum CRC calculation time specifications. 

The maximum and minimum time is calculated based on a minimum divisor and a maximum divisor settings as well as the process, voltage, and temperature (PVT) variation of the internal oscillator.

The available divisor settings are:

1. Arria II and Stratix IV devices: 1, 2, 3, 4, 5, 6, 7, 8
2. Cyclone III, Cyclone IV, Cyclone V, Arria V, and Stratix V devices: 0, 1, 2, 3, 4, 5, 6, 7, 8

If you set the divisor in between minimum and maximum, you may calculate the CRC calculation time based on the formula provided in the workaround below.

Resolution

For Arria II and Stratix IV devices:
Maximum Time (n) = 2^(n-8) * Maximum Time
Minimum Time (n) = 2^(n-1) * Minimum Time

For Cyclone III, Cyclone IV, Cyclone V, Arria V, and Stratix V devices:
Maximum Time (n) = 2^(n-8) * Maximum Time
Minimum Time (n) = 2^n * Minimum Time

Related Products

This article applies to 19 products

Arria® II GX FPGA
Cyclone® V E FPGA
Cyclone® V ST SoC FPGA
Cyclone® V SX SoC FPGA
Arria® V GT FPGA
Arria® V GX FPGA
Arria® V GZ FPGA
Arria® II GZ FPGA
Cyclone® III FPGAs
Cyclone® III LS FPGA
Cyclone® IV E FPGA
Cyclone® IV GX FPGA
Stratix® IV E FPGA
Stratix® IV GT FPGA
Stratix® IV GX FPGA
Stratix® V E FPGA
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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