Article ID: 000085045 Content Type: Troubleshooting Last Reviewed: 02/05/2014

Does the Stratix V Hard IP for PCI Express support Gen3 Phase 2 and Phase 3 equalization in simulation?

Environment

    PCI Express
    Simulation
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Description

The auto generated Stratix® V Hard IP for PCI Express® test bench Root Port bus functional model (BFM) bypasses Gen3 Phase 2 and Phase 3 Equalization.

If using a third-party Root Port BFM, modify it to terminate Equalization after Phase 0 and Phase 1
have completed.

Resolution

 

Related Products

This article applies to 1 products

Stratix® V GX FPGA

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