Description
This error may occur in the Cadence NC family of simulators when you turn on Maintain Hierarchy on the Simulation page of the Settings dialog box in the Quartus® II software version 4.0.
This error is fixed beginning with the Quartus II software version 4.1.
To avoid this error in version 4.0, from the Assignments menu, choose Settings. On the Simulation page, turn off Maintain Hierarchy. Generate a new Verilog Output File (.vo) for gate-level simulation.