Half-Rate Clock Not Connected When Clock Sharing is Enabled

If you generate a memory controller with the High Performance Controller II and Multiple Controller Clock Sharing options enabled in SOPC Builder, the half-rate clock is not connected.

This issue affects all designs that use the high-performance controller II architecture with the Multiple Controller Clock Sharing option enabled in SOPC Builder.

The internal half-rate bridge for the sharing PLL controller does not function.

To connect the half-rate clock, perform the following steps:

1. Edit the sharing PLL controller top-level file to include the half-rate clock input port as in the following example:

Verilog HDL

module <variation name> (sys_clk_in,sys_half_clk_in,soft_reset_n,input sys_clk_in;input sys_half_clk_in;input soft_reset_n;.sys_clk_in(sys_clk_in),.sys_half_clk_in(sys_half_clk_in),.soft_reset_n(soft_reset_n),

VHDL

ENTITY <variation name_master> ISPORT (sys_clk_in : IN STD_LOGIC;sys_half_clk_in : IN STD_LOGIC; soft_reset_n : IN STD_LOGIC;COMPONENT <variation name>_controller_phyPORT (sys_clk_in : IN STD_LOGIC;sys_half_clk_in : IN STD_LOGIC; soft_reset_n : IN STD_LOGIC;sys_clk_in => sys_clk_in,sys_half_clk_in => sys_half_clk_in,aux_full_rate_clk => aux_full_rate_clk,

2. Edit the SOPC top-level file to connect the half-rate clock from the source to the sharing controller as in the following example:

Verilog HDL

<variation name> the_ <variation name>(.soft_reset_n (clk_0_reset_n),.sys_half_clk_in ( <variation name_master>_aux_half_rate_clk_out),.sys_clk_in (<variation name_master>_phy_clk_out)

VHDL

component <variation name> is port (-- inputs:signal soft_reset_n : IN STD_LOGIC;signal sys_half_clk_in : IN STD_LOGIC;signal sys_clk_in : IN STD_LOGIC;the_<variation name> : <variation name>port map(soft_reset_n => clk_0_reset_n,sys_half_clk_in => out_clk_<variation name_master>_aux_half_rate_clk,sys_clk_in => internal_<variation name_master>_phy_clk_out

This issue will be fixed in a future version.