Article ID: 000085024 Content Type: Troubleshooting Last Reviewed: 10/17/2011

Implementation of ALTGX megafunction in Deterministic Latency mode might generate a warning message in the Quartus II software for Cyclone IV GX

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If you implement an ALTGX megafunction in Deterministic Latency mode, the Quartus II software might generate messages similar to the following:Warning (10541): VHDL Signal Declaration warning at c4gx_test.vhd(62): used implicit default value for signal "pll_reconfig_done" because signal was never assigned a value or an explicit default value. Use of implicit default value may introduce unintended design optimizations.Warning (10036): Verilog HDL or VHDL warning at c4gx_test.vhd(142): object "wire_receive_pcs0_signaldetect" assigned a value but never read

    Resolution

    You may safely ignore these messages.

    Related Products

    This article applies to 1 products

    Cyclone® IV FPGAs

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