Article ID: 000085022 Content Type: Product Information & Documentation Last Reviewed: 08/13/2012

How do I train a Cyclone III LVDS receiver if control characters are not present in the transmitter datastream?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

If control characters are not available in the transmitter datastream, the following option is available when setting up an LVDS receiver in Cyclone® III devices.

 

If the reference clock is the data rate / deserialization factor (one rising edge per serial word), then the word boundary is deterministic. For example if your system contains 800Mbps x8 SERDES data and the received clock is 100MHz, then for every one rising edge of the reference clock, you receive one 8 bit serial word.  Using timing simulation, you can determine the default bit position in the word that this interface will have on power up, or after areset is applied to the PLL.

 

If the reference clock is not stable when the device configures, the PLL phase shifts can be random, which could lead to random word alignment.  Reset the PLL to get back to a deterministic position. The best guidance for free running data is to use a clock that gives you the deterministic relationship with word alignment.  Using timing simulation, or lab measurements, you can determine how many bit slip pulses are required to apply to the data alignment circuit to properly align the words. Then build a simple state machine to implement those bit slip pulses after the PLL lock is asserted and stable whether it is after the asynchronous reset or on power up when the device enters user mode.

Related Products

This article applies to 1 products

Cyclone® III FPGAs

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