Article ID: 000084984 Content Type: Troubleshooting Last Reviewed: 07/27/2023

Incorrect Port Direction for SerialLite II IP Core Targeting Arria® V, Cyclone® V, and Stratix® V Devices

Environment

    Intel® Quartus® Prime Standard Edition
    SerialLite II v18.1
BUILT IN - ARTICLE INTRO SECOND COMPONENT

Critical Issue

Description

The SerialLite II IP core incorrectly sets the direction for the err_rr_8berrdet port as the output port. This issue affects Arria® V, Cyclone® V, and Stratix® V devices.

 

 

Resolution

To work around this issue, change the direction of the err_rr_8berrdet port to input and connect the port to the rx_errdetect output port of the Custom PHY transceiver.

This problem has been fixed in version 18.1 of the SerialLite II IP core.

Related Products

This article applies to 8 products

Arria® V GT FPGA
Arria® V GX FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA
Cyclone® V FPGAs and SoC FPGAs
Stratix® V GS FPGA
Stratix® V GT FPGA
Stratix® V GX FPGA

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