Article ID: 000084964 Content Type: Troubleshooting Last Reviewed: 08/18/2012

DDR2 Interfaces Using Soft Memory Controller May Not Close Timing When Targeting Arria V or Cyclone V Devices

Environment

    Quartus® II Subscription Edition
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Critical Issue

Description

This problem affects DDR2 and LPDDR2 products.

Interfaces using the soft memory controller may fail to close timing on Arria V and Cyclone V devices.

Resolution

The workaround for this issue is to use a different fitter seed.

This issue will be fixed in a future version.

Related Products

This article applies to 2 products

Arria® V FPGAs and SoC FPGAs
Cyclone® V FPGAs and SoC FPGAs

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