The EDCRC circuitry Fmax for Cyclone® V devices is different according to the density. Hence the appropriate minimum clock divisor value needs to be set to compensate for this difference. EDCRC might fail if the divisor value used is lower than the minimum value.
Affected devices:
Cyclone V FPGA
| Device Variant | Member Code | Minimum Clock Divisor |
|---|---|---|
| Non-SoC | A5, C4, C5, D5 | 2 |
| SoC | A2, A4, C2, C4 | 2 |
| Non-SoC | C3 | 4 |
| Non-SoC | A2, A4 | 2 |
| SoC and Non-Soc | Others | 1 |
For Quartus® Prime software versions 16.0.2 and earlier :
Choose the correct minimum clock divisor to ensure that the EDCRC works correctly. There will be no impact for devices that have been deployed to field if the EDCRC is passing.
For Quartus Prime versions later than 16.0.2 :
The Quartus Prime software will automatically detect an invalid divisor value, change it to a valid value and provide a warning message to the user. For example if using a 5CEFA2F31C7N and 1 is chosen as the minimum clock divisor value, the following warning message will appear during compilation:
"Real-time CRC ERROR_CHECK_FREQUENCY_DIVISOR VALUE(2) in design does not match value (1) in the Quartus Prime Settings File"