Article ID: 000084933 Content Type: Troubleshooting Last Reviewed: 08/13/2012

Are Stratix IV GX/GT devices compliant with the PCI Express transmitter jitter specification when operating in Gen2 x8 mode?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

No. Stratix® IV GX/GT device characterization data shows that the transmitter jitter is 65ps when operating in Gen2 x8 mode and using a CMU PLL. The PCI Express specification requires 50ps max jitter.

To meet the PCI Express specification the ATX PLL must be used. The ATX PLL is not available for use in the PCI Express IP in Quartus® II software versions 9.1 SP2 and earlier. This feature will be made available in a future release of the Quartus II software.

To ensure that your design will meet the specification with the ATX PLL you must:

  1. Locate the ATX PLL is between the two x4 transciever blocks.
  2. Locate the REFCLK for the ATX PLL in the lower transciever block.

PCI Express Gen2 x1/x4 and all Gen1 configurations are not impacted.

Stratix IV GX/GT devices operating in PCI Express Gen2 x8 mode using the CMU PLL are compatible but not compliant with the PCI Express Specification.

Related Products

This article applies to 2 products

Stratix® IV GT FPGA
Stratix® IV GX FPGA

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