Article ID: 000084931 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Is there any issue with DDR, DDR2, DDR3 SDRAM High Performance controller generated testbench regarding dm_delayed signal?

Environment

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Description

Altera® Quartus® II software and DDR, DDR2, DDR3 SDRAM High Performance Controller IP versions 7.0 to 9.1 Megawizard generated testbench uses dm_delayed signal that is delayed by one time unit defined in the testbench. That delay needs to taken out from the testbench file.

This issue will be corrected in the future version of the Quartus II software and the IP.

To fix this problem, search for dm_delayed in the testbench and in the statement below change:

wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] #(GATE_BOARD_CLK_DELAY * 1 1) dm_delayed;

to

wire[gLOCAL_DATA_BITS / DWIDTH_RATIO / gMEM_DQ_PER_DQS - 1:0] dm_delayed;

Related Products

This article applies to 9 products

Cyclone® III FPGAs
Arria® GX FPGA
Stratix® II GX FPGA
Stratix® II FPGAs
Stratix® IV GX FPGA
Stratix® III FPGAs
Arria® II GX FPGA
Stratix® IV GT FPGA
Stratix® IV E FPGA

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