Article ID: 000084896 Content Type: Troubleshooting Last Reviewed: 02/26/2013

Why can't I pack my second pipeline register of sload signal into the DSP Block when inferring the mult_accum functionality?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When the customer infers the mult_accum module, they will find that the second pipeline register of the sload signal cannot be packed into the DSP Block.  This will affect timing analysis results.

Resolution

To work around this issue, use the ALTMULT_ACCUM MegaCore® to preform the register packing.

Related Products

This article applies to 2 products

Arria® V FPGAs and SoC FPGAs
Stratix® V GX FPGA

Disclaimer

1

All postings and use of the content on this site are subject to Intel.com Terms of Use.