Article ID: 000084885 Content Type: Troubleshooting Last Reviewed: 07/01/2015

Why does my PCIe Development Kit not enumerate and/or show up on the link after loading an SOF programming file?

Environment

    PCI Express
BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description Due to an issue with some BIOS and some OS, notably CentOS 6, the link cannot automatically enumerate the Altera® Hard IP for PCI® Express if the FPGA is configured after the BIOS/OS discovery phase has completed.
Resolution

Press the reset button on the motherboard so that a warm reset occurs (one in which the power is kept on so the FPGA image is retained). In most cases this should cause the BIOS/OS to re-discover connected devices and allow the FPGA to be seen on the PCIe link.

Alternatively, ensure that the dev kit is configured before the BIOS/OS discovery phase starts from cold reset (within 100ms). To do this either power the dev kit externally and only power on the motherboard once the FPGA is configured or ensure the FPGA is configured using FPP mode.

Related Products

This article applies to 16 products

Stratix® V GX FPGA
Cyclone® V ST SoC FPGA
Arria® V GX FPGA
Cyclone® V SX SoC FPGA
Stratix® V GS FPGA
Cyclone® V GT FPGA
Stratix® V GT FPGA
Arria® V GZ FPGA
Cyclone® V GX FPGA
Cyclone® V SE SoC FPGA
Stratix® V E FPGA
Intel® Arria® 10 GX FPGA
Intel® Arria® 10 SX SoC FPGA
Intel® Arria® 10 GT FPGA
Arria® V ST SoC FPGA
Arria® V SX SoC FPGA

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