Article ID: 000084848 Content Type: Troubleshooting Last Reviewed: 09/11/2012

Why does the PCIe core return Unsupported Request for Type0 Configuration Read request?

Environment

BUILT IN - ARTICLE INTRO SECOND COMPONENT
Description

When the PCIe® core is configured as End Point (EP),  its Completer ID in configuration space is assigned by the type0 Configuration Write request (CfgWr0). Subsequent type0 Configuration Read requests (CfgRd0) must use this Completer ID in the third dword of TLP header format. 

If the host sends CfgRd0 request with Completion ID different from the value given by the previous CfgWr0, the core will respond with Unsupported Request Completion message. 

To fix this problem, please make sure that the Completer ID in CfgRD0 request must be the same as the value assigned by its previous CfgWr0.

Related Products

This article applies to 6 products

Arria® II GX FPGA
Arria® II GZ FPGA
Stratix® IV GX FPGA
Stratix® IV GT FPGA
Stratix® V GX FPGA
Cyclone® IV GX FPGA

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