Article ID: 000084837 Content Type: Troubleshooting Last Reviewed: 10/09/2013

Why can the LVDS I/O not be selected in the Triple Speed Ethernet MegaCore GUI for Cyclone series devices?

Environment

  • Cyclone® II FPGA
  • Cyclone® IV GX FPGA
  • Cyclone® III FPGAs
  • Cyclone® III LS FPGA
  • Cyclone® IV E FPGA
  • Cyclone® V GT FPGA
  • Cyclone® V E FPGA
  • Cyclone® V GX FPGA
  • Cyclone® V SE SoC FPGA
  • Cyclone® V ST SoC FPGA
  • Cyclone® V SX SoC FPGA
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Description LVDS I/O cannot be selected in the Triple Speed Ethernet MegaCore® GUI if the target device is a Cyclone® series device. This is because the LVDS serializer and deserializers (SerDes) cannot support 1.25 Gbps data rates required by Triple Speed Ethernet. 
Resolution

 

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