Article ID: 000084805 Content Type: Troubleshooting Last Reviewed: 05/20/2013

CPRI IP Core Variations Configured with the All Mapping Mode Might Not Achieve Timing Closure

Environment

  • Quartus® II Subscription Edition
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT

    Critical Issue

    Description

    If your CPRI IP core variation is configured with Mapping mode set to All, and the target device family and CPRI line rate are set to any of the following combinations, you may observe setup time violations in the CPRI Rx MAP block and the CPRI Tx MAP block.

    These timing violations have been observed in the following combinations of target device family and CPRI line rate:

    • Arria V device at CPRI line rate 4.9152 Gbps
    • Arria V device at CPRI line rate 6.144 Gbps
    • Stratix V device at CPRI line rate 9.8304 Gbps
    Resolution

    To avoid this issue, configure your CPRI IP core with the specific MAP interface mapping mode your design requires (Basic, Advanced 1, Advanced 2, or Advanced 3) instead of the All setting.

    However, refer to Some CPRI IP Core Variations Configured with the Advanced 1 Mapping Mode Might Not Achieve Timing Closure.

    This issue is fixed in version 12.1 of the CPRI MegaCore function.

    Related Products

    This article applies to 2 products

    Arria® V FPGAs and SoC FPGAs
    Stratix® V FPGAs

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