Description
When the Arria® 10 Hard IP for PCI Express® transmits packets, its link partner may report bad TLPs or bad DLLPs. These Correctable Errors may result in lower throughput. An incorrect Hard IP bit setting causes these errors.
Resolution
If using Quartus® Prime v15.1.2, patch 2.03r can be obtained via MySupport.
This problem has been fixed in Quartus Prime 16.0. Upgrade and regenerate the PCIe® Hard IP core and recompile your design.